The present invention relates to a semiconductor memory and, more particularly, to an SRAM (static random access memory) suitable for high-speed operation.
For its short access time and cycle time, the SRAM is utilized extensively as a cache memory in computer systems. As such, the SRAM constitutes a key component that holds sway on the speed and performance of the computer system. Efforts of research and development have been under way primarily to boost the operating speed of the memory.
FIG. 2 is a circuit diagram of a conventional SRAM memory cell array and a read/write circuit composed of CMOSs.
A memory cell MC0 comprises a flip-flop and transfer MOS transistors MT0 and MT1. The flip-flop has two CMOS inverters connected alternately, one inverter composed of transistors MI0 and MI1; the other inverter made of transistors MI2 and MI3. Bit line loads ML0 and ML1 as well as transistors MR0, MR1 and MEQ constitute a bit line recovery circuit BR which is connected to bit lines. The bit lines are also connected to a bit line pull-down circuit and a sense amplifier SA via switch transistors MY0 and MY1. The bit line pull-down circuit comprises transistors MD0 and MD1.
To read data from a memory cell requires driving High word-line and bit-line select signals (e.g., W0 and YS in FIG. 2) on the word line and bit lines connected to the cell in question. The signals bring the memory cell MC0 into a selected state. Depending on the data stored in the cell, a current (called a memory cell current) flows from either of the bit lines to the memory cell MC0. The current lowers the bit line potential and creates a potential difference between the bit lines B0 and B1. The potential difference is transmitted via the switch transistors MY0 and MY1 to the sense amplifier SA for amplification. In turn, the sense amplifier SA outputs the amplified potential difference as a data output signal DO via an output buffer OB.
To write data to a memory cell involves selecting the cell in question using the above procedure. Depending on the data to be written, one of write signals WD0 and WD1 is driven High. This causes the bit line pull-down circuit to bring either of the bit lines Low, allowing the data to be written to the memory cell.
For conventional SRAMs, the bit line recovery circuit BR is controlled primarily by one of two methods. The first control method involves using transistors ML0 and ML1 as bit line loads for a write operation, and utilizing the bit line recovery circuit BR to recover the bit lines for bit line equalization and write operations. This method is characterized in that it equalizes or recovers the bit lines prior to a word line transition in a read or a write cycle.
Illustratively, as shown in FIG. 3, a control signal CBR is driven Low before the word line W0 is brought High (i.e., into selected state). This causes the transistors MR0, MR1 and MEQ of the bit line recovery circuit BR to conduct, pulling both bit lines B0 and B1 up to a supply voltage VCC in preparation for the next cycle.
In a read operation, the transistors MR0, MR1 and MEQ of the bit line recovery circuit do not conduct, and the transistors ML0 and ML1 work as bit line loads. Generally, high-speed amplification is made possible using a CMOS- or bipolar transistor-based sense amplifier provided the bit line signal amplitude is about 50 mV. If the memory cell current is 100 .mu.A, the equivalent resistance of the transistors ML0 and ML1 should be designed to be about 500 .OMEGA. in order to obtain the above-mentioned bit line signal amplitude.
With the first control method in use, the time required for bit line recovery is determined by the gate width of the transistors MR0, MR1 and MEQ of the bit line recovery circuit BR. It follows that designing a sufficient gate width for these transistors will reduce the equivalent resistance (e.g., to about 100 .OMEGA.) and shorten the bit line recovery time.
On the other hand, after the write signal WD0 is brought back Low, the control signal CBR of the bit line recovery circuit needs to be driven Low. That is because driving the control signal CBR Low before the write signal WD0 is brought back Low will let a large through current flow from the transistor MR0 past the transistors MY0 and MD0 promoting power dissipation.
A change from the low to the high potential of the control signal CBR must occur earlier than a word line switchover of the next cycle. If the control signal CBR rises later than the word line transition, the bit lines remain equalized even after the transition, which will cause delays in data read-out. For these reasons, the first method requires interposing timing margins between the write signal WD0 and the control signal CBR, and between the control signal CBR and the word line select signal. The presence of such timing margins has made it difficult for conventional SRAMs to shorten the write cycle time.
The second control method for the bit line recovery circuit BR involves using the bit line recovery circuit BR to load the bit lines in a read operation and to recover them in a write operation. As an advantage, this second method has no need for timing margins between the write signal WD0 and the control signal CBR. Because the bit line recovery circuit BR is used as bit line loads, the transistors ML0 and ML1 may be omitted.
With the second control method, as shown in FIG. 4, the control signal CBR is usually at the low potential and is brought High only while the write signal WD0 is being High. Thus even in a read cycle, the transistors MR0, MR1 and MEQ of the bit line recovery circuit BR conduct and work as bit line loads. If the memory cell current is assumed to be as large as its counterpart mentioned above, the equivalent resistance of the transistors MR0 and MR1 should be designed to be about 500 .OMEGA.. This means that the second control method requires a longer bit line recovery time than the first method. Thus it is also difficult for the second control method to shorten the write cycle time.
As described, the conventional techniques, be they the first or the second control method above, have had difficulty in shortening the cycle time. Examples utilizing the above-mentioned first control method include an SRAM discussed in the IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, April 1993, pp. 478-483, and semiconductor memories disclosed in Japanese Unexamined Patent Publications Nos. Hei 4-113590 and Hei 4-344393.
The disclosures of the cited patent applications Hei 4-113590 and Hei 4-344393 may appear structurally similar to embodiments of this invention, to be described later. However the semiconductor memory of Japanese Unexamined Patent Publication No. Hei 4-113590 is intended to provide against those pulse width fluctuations of the control signal CBR which are attributable to environmental variations and fabrication irregularities, and does not address the shortening of timing margins for the control signal, which is an object of this invention.
Furthermore, the semiconductor memory of Japanese Unexamined Patent Publication No. Hei 4-344393 is intended to enlarge the bit line signal amplitude at the time of a read operation, and has nothing to offer in terms of shortening the control signal timing margins.
An example utilizing the second control method above includes an SRAM discussed in the IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990, pp. 1049-1055.